This invention relates generally to the field of data processing systems, and more particularly, to data processing systems that schedule the execution of requests to increase system performance.
Most modem data processing systems include at least one processor and one memory. The processor is typically connected to the memory via a system bus or the like. Other components may also be connected to the system bus including, for example, input/output (I/O) modules, other processors, and/or other memory devices. During normal functional operation of the system, the processor executes a series of commands to accomplish a desired result. Some of these commands can result in requests to the memory, including read requests and write requests. The requests provided by the processor are typically issued in the order of processor execution.
A read request typically provides a read address to the memory over the system bus. The memory reads the requested data from the location identified by the read address and returns the requested data to the processor for subsequent processing. Typically, the processor cannot process further commands until the return data is received by the processor.
In contrast to a read request, a write request typically provides a write address and a write data packet to the memory over the system bus. The memory writes the write data packet to the write address, and no return data is typically expected. Thus for a write request, the processor can typically continue processing further commands immediately after the write request is provided to the system bus and/or memory.
In many systems, the system bus operates at a lower speed than the processor. In addition, more than one system component may compete for the system bus and/or memory. For these and other reasons, the requests issued by the processor may not be immediately serviced by the memory, thereby reducing the performance of the system.
One way to improve system performance is to provide a write queue between the processor and the system. As indicated above, no return data is typically expected for write requests, and the processor can typically continue processing further commands immediately after the write request is provided to the write queue. The write queue is used to temporarily store the write requests until the memory and/or system bus can service the write requests. This frees up the processor more quickly because the write queue, rather than the processor, is left waiting for the system bus and/or memory.
U.S. Pat. No. 5,790,813 to Wittaker discloses a pre-arbitration system and look-around circuit for increasing the throughput of a data processing system by allowing read requests to be executed prior to previously issued write requests so long as the data coherency of the system is not compromised. As noted above, read requests can slow processor throughput by not allowing the processor to process further commands until the read data is returned from the memory. Write requests, on the other hand, typically do not prevent the processor from processing further commands after the write request is issued. Thus, by assigning a higher priority to read requests relative to write requests, Wittaker suggests that the overall throughput of the data processing system may be increased.
While Wittaker provides some increased throughput by assigning a higher priority to read requests, Wittaker does not appear to reduce the overall bus traffic. Rather, it appears each request of Wittaker must eventually be processed over the system bus. It would be desirable to provide a system whereby selected requests can be replaced with substitute requests that perform substantially the same end function, but reduce the overall bus traffic to achieve increased system performance.